1. Technical Field
The present invention relates to an amplifier, and more particularly, to a high power amplifier system employed in, e.g., a transmitting portion of a code division multiple access (CDMA) terminal, which provides high dynamic range and minimizes power consumption.
2. Description of Related Art
Code division multiple access (CDMA) is a method for providing multiple-access within the same frequency using spread spectrum technology. Most CDMA functions are embodied in hardware and software in a modem chip and every radio frequency (RF) circuit comprises a plurality of monolithic microwave integrated circuit (MMIC) chips. Each of the MMIC chips is a high-frequency integrated circuit that is manufactured by forming passive devices such as resistors, inductors and capacitors, as well as active devices such as transistors and a field effect transistors (FET), on one semiconductor substrate. MMIC chips can perform a variety of functions such as signal amplification and frequency conversion.
Prior to transmission of a signal from a terminal to a base station, the signal is preferably passed through an RF filter and then amplified to an appropriate level. Signal amplification is typically performed using a variable gain amplifier (VGA).
FIG. 1 is a circuit diagram of a conventional variable gain amplifier. The variable gain amplifier comprises three transistors NPN1, NPN2 and NPN3 and two impedance components ZL and Ze. The transistor NPN3 has a base that receives an alternating current (AC) input signal Vin that varies about a fixed direct current (DC) bias voltage Vs. Control voltages having a potential difference xcex94V are input to the bases of transistors NPN1 and NPN2 to control the gain of the variable gain amplifier. The two impedance components ZL and Ze are employed for controlling the gain of the variable gain amplifier. The voltage gain AV of an output signal VO with respect to the input signal Vin of the circuit can be expressed by formula (1):                               A          V                =                                            V              O                        Vin                    ≅                                                                      g                  m                                ⁢                                  Z                  L                                                            1                +                                                      g                    m                                    ⁢                                      Z                    e                                                                        xc3x97                          1                              1                +                                  e                                      -                                                                  Δ                        ⁢                                                  xe2x80x83                                                ⁢                        V                                                                    V                        T                                                                                                                                                    (        1        )            
where       g    m    =                    I        ee                    V        T              .  
Referring to formula (1) and FIG. 1, in the conventional variable gain amplifier, the bias current Iee is fixed to a particular level by the DC bias voltage VS, and thus, the gain AV is controlled by adjustment of the potential difference xcex94V between the two control voltages.
A circuit that is used in a CDMA RF transmitting portion must have sufficient linearity to satisfy recommendations on adjacent channel power ratio (ACPR). ACPR indicates a ratio of the maximum value of signal power transmitted from an assigned frequency band, that is, a corresponding channel, with respect to power in a different channel affected by the signal power. Particularly, as the power of the transmitted signal becomes closer to the maximum permissible power value, it becomes increasingly difficult to satisfy the recommendations. Indeed, if output power reaches almost the maximum power value, the power of a signal affecting a peripheral frequency band increases more significantly than the power of the transmitted signal, and thus, the ACPR value decreases.
To solve this problem, a large amount of bias current should be supplied. On the other hand, in a case where the electric power of the transmitted signal is low, the ACPR value increases, so that the ACPR recommendations can be sufficiently satisfied.
One requirement of the ACPR recommendations, however, is for a transmitted signal to have a particular power value irrespective of the electric power of the transmitted signal. Thus, in the prior art, a considerable amount of bias current Iee should continually be supplied to the amplification circuit in order to satisfy the ACPR recommendations. Consequently, the conventional amplification scheme provides a disadvantage in terms of electric power consumption.
To solve the above problems, it is an object of the present invention to provide a high power amplification system which has a sufficient dynamic range to satisfy ACPR recommendations and is capable of minimizing power consumption.
Accordingly, to achieve the above object, there is provided a high power amplifier system including a voltage-to-current converter which outputs current in proportion to the difference voltage between a reference voltage and a first control voltage for controlling gain; a difference voltage generator which outputs a second control voltage and a third control voltage in response to the output current of the voltage-to-current converter, wherein the difference between the second control voltage and third control voltage is the same as the difference between the reference voltage and the first control voltage; a bias control circuit which outputs bias control current through an output terminal in response to the output current of the voltage-to-current converter and at least one control signal; a resistance component having one end to which the output current of the bias control circuit is applied and the other end which is connected to an input terminal; and an amplification circuit amplifying the input signal which is received through the input terminal and varies about the output current of the bias control circuit applied through the resistance component in response to the second and third control voltages. The bias control circuit magnifies the amount of current flowing in the amplification circuit in a case where the first control voltage, that is, the gain of the amplification circuit, has a high voltage value within a predetermined voltage range, reduces the amount of current flowing in the amplification circuit in a case where the first control voltage, that is, the gain of the amplification circuit, is low and controls the bias control current in order to make a particular amount of current flow in a case where the first control voltage is over the predetermined voltage range. Therefore, the bias control circuit makes the bias control current maintain superior linearity within a predetermined voltage range of the first control voltage. In addition, in a case the first control voltage is over the predetermined voltage range, the bias control circuit controls the bias control current so that a particular amount of current can flow in the amplification circuit, and thus the current flowing in the amplification circuit can be minimized.
In another aspect of the present invention, the bias control circuit comprises a maximum/minimum current selection circuit which receives at least one control signal, selects the maximum current and the minimum current, outputs the selected maximum current and introduces the difference current between the maximum current and the minimum current; a first difference current generating circuit which supplies the difference current between the maximum and minimum currents to the maximum/minimum current selection circuit, and mirrors and outputs the supplied difference current; a Fermi-Dirac function generating circuit which generates current which is in proportion to the Fermi-Dirac function in response to the output current of the first difference current generating circuit and the output current of the voltage-to-current converter; and a second difference current generating circuit which generates and outputs the difference current between the output current of the Fermi-Dirac function generating circuit and the maximum current.
In yet another aspect of the present invention, the maximum/minimum current selection circuit comprises a plurality of maximum current sources which supplies the maximum currents, each of the maximum currents having a different size; a plurality of minimum current sources which supplies the minimum currents, each of the minimum currents having a different size; a first switch which selects one from among the plurality of the maximum current sources in response to a control signal; a second switch which selects one from among the plurality of the minimum current sources in response to the control signal or another control signal; a difference current entrance terminal which receives the difference current between the maximum current selected by the first switch and the minimum current selected by the second switch; a first bipolar transistor one end of which is connected to the first switch and the base of the first bipolar transistor and the other end of which is connected to supply power voltage; and a second bipolar transistor one end of which is connected to the second switch and the difference current entrance terminal, the base of which is connected to the base of the first bipolar transistor and the other end of which is connected to the supply power voltage ground.
In another aspect, the first current generating circuit comprises a first MOS transistor which one end of which is connected to supply power voltage and the other end of which is connected to the gate of the first MOS transistor and supplies the difference current between the maximum current and the minimum current selected in the maximum/minimum current selection circuit through the difference current entrance terminal, a second MOS transistor one end of which is connected to the supply power voltage and a gate of which is connected to the gate of the first MOS transistor and mirrors the difference current flowing in the first MOS transistor, a third bipolar transistor one end of which is connected to the base of the third transistor and the other end of the second MOS transistor and the other end of which is connected to the supply power voltage.
In yet another aspect, the Fermi-Dirac function generating circuit comprises a fourth bipolar transistor one end of which is connected to the supply power voltage and the base of which the output current of the voltage-to-current converter is applied to; a third MOS transistor one end of which is connected to the supply power voltage and the other end of which is connected to the gate of the third MOS transistor; a fifth bipolar transistor one end of which is connected to the other end of the third MOS transistor and the other end of which is connected to the other end of the fourth bipolar transistor; a second resistance component one end of which the output current of the voltage-to-current converter is applied to and the other end of which is connected to the base of the fifth bipolar transistor; a sixth bipolar transistor one end of which is connected to the other end of the fourth bipolar transistor and the other end of the fifth bipolar transistor, the other end of which is connected to the supply power voltage and the base of which receives the mirrored output current of the first difference current generating circuit; a first diode whose input terminal is connected to the other end of the second resistance component; and a third resistance component one end of which is connected to an output terminal of the first diode and the other end of which is connected to the supply power voltage.
In another aspect, the second current generating circuit comprises a fourth MOS transistor, a fifth MOS transistor, a seventh bipolar transistor, a sixth MOS transistor, a eighth bipolar transistor, a fifth resistance component and a fourth impedance component. One end of the fourth MOS transistor is connected to the supply power voltage and the gate of the fourth MOS transistor is connected to the gate of the third MOS transistor. One end of the fifth MOS transistor is connected to the supply power voltage and the other end of the fifth MOS transistor is connected to the gate of the fifth MOS transistor and the other end of the fourth MOS transistor. One end of the seventh bipolar transistor is connected to the other end of the fourth MOS transistor and the other end of the fifth MOS transistor and the other end of the seventh bipolar transistor is connected to the supply power voltage. The output current of the maximum/minimum current selection circuit is applied to the base of the seventh bipolar transistor. One end of the sixth MOS transistor is connected to the supply power voltage and the gate of the sixth MOS transistor is connected to the gate of the fifth MOS transistor. One end of the eighth bipolar transistor is connected to the other end of the sixth MOS transistor and an output terminal. One end of the fifth resistance component is connected to the base of the eighth bipolar transistor and the other end of the fifth resistance component is connected to the other end of the sixth MOS transistor. One end of the fourth impedance component is connected to the other end of the eighth bipolar transistor and the other end of the fourth impedance component is connected to the supply power voltage ground.
In yet another aspect of the present invention, a method for controlling bias current in an amplifier comprises the steps of: applying a control voltage to an amplifier for controlling the gain of the amplifier; generating a bias control current for biasing the amplifier; and dynamically adjusting the magnitude of the bias control current based on the magnitude of the control voltage to thereby minimize power consumption of the amplifier. Preferably, the step of dynamically adjusting the magnitude of the bias control current comprises the steps of: linearly reducing the magnitude of the bias control current as the control voltage decreases within a predetermined range of control voltages; and linearly increasing the magnitude of the bias control current as the control voltage increases within a predetermined range of control voltages. Further, the magnitude of the bias control current is maintained to a fixed value as the control voltage varies outside a predetermined range of control voltages.
In another aspect of the present invention, the step of generating a bias control current for biasing the amplifier comprises the steps of: selecting a maximum and minimum current in response to a selection control signal; generating a difference current having a magnitude substantially equal to the difference between the selected maximum and minimum currents; and generating a bias control current based on the difference current using a linear function.
These and other aspects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments, which is to be read in connection with the accompanying drawings.